Radar work experience

phased array wave front example with reflection

VHDL

VHDL is a language that is used to describe the layout of logic gates for a PLD on a VHSIC.
There is a hierarchy of PLD's; SPLD, GAL, CPLD, FPGA.
FPGA's are used for low production runs and high modifiability for future updates. This is because they are a customisable array of logic gates, that can be connected however you like, to make whatever combinational logic signal processing you want.
Another use case is during the development of ASIC designs to reduce the prototyping cycle time.
VHDL and FPGA's originate from a US DOD project from the early 1980s.

Logic Gates

Buffer

A Buffer is an electronic circuit element used to isolate an input from an output. The buffer's output state mirrors the input state.
buffer

Input	Output
A	Q
0
1

Not

A Not gate or an inverter is a logic gate which implements logical negation. It outputs a bit opposite of the bit that is put into it.

Input	Output
A	Q
0
1

And

The And gate is a basic digital logic gate that implements logical conjunction. A high output (1) results only if all the inputs to the and gate are high (1). If not all inputs to the and gate are high, low output results.

Input1	Input2	Output
A	B	Q
0	0
0	1
1	0
1	1

Or

The Or gate is a digital logic gate that implements logical disjunction. It outputs a 1 if any inputs are 1, or outputs a 0 only if all inputs are 0.
or gate

Input1	Input2	Output
A	B	Q
0	0
0	1
1	0
1	1

Nand

A Nand gate (not-and) is a logic gate which produces an output which is false, only if all its inputs are true; thus its output is complement to that of an And gate.

Input1	Input2	Output
A	B	Q
0	0
0	1
1	0
1	1

Nor

The Nor gate is a digital logic gate which produces a high output (1) result if both the inputs to the gate are low (0). If one or both input is high (1), a low output (0) results; thus its output is complement to that of an Or gate.

Input1	Input2	Output
A	B	Q
0	0
0	1
1	0
1	1

Xor

The Xor(Exclusive Or) gate is a digital logic gate that gives a true (1 or high) output when the number of true inputs is odd. An Xor gate implements an exclusive or; that is, a true output results if one, and only one, of the inputs to the gate is true. If both inputs are false (0/low) or both are true, a false output results.

Input1	Input2	Output
A	B	Q
0	0
0	1
1	0
1	1

Xnor

The Xnor gate is a digital logic gate whose function is the logical complement of the Exclusive Or (Xor) gate.

Input1	Input2	Output
A	B	Q
0	0
0	1
1	0
1	1

Now try some where there is more than one gate.

Half adder

half adder

Input		Output
A	B	Sum	Carry
0	0
0	1
1	0
1	1

Adder

adder

Input			Output
A	B	Carry in	Sum	Carry
0	0	0
0	0	1
0	1	0
0	1	1
1	0	0
1	0	1
1	1	0
1	1	1

Binary

Counting

Counting in binary can seem a bit daunting but it's not really any different to normal decimal counting.
When you were first learning numbers you'd have been taught about the unit's ten's hundred's columns system.

Hundred's	Ten's	Unit's
1	0	5

Binary is basically the same, but instead of have multiple options (0 up to 9 in decimal) it only has 2, so each column is basically a tick box for it's value.
The values go up in powers of 2 e.g. 1,2,4,8,16,32,64,128,256,1024,2048...

To convert a number from decimal to binary you can:

Pick the biggest power of 2 that is less than or equal to the number you're converting and put a 1 in that column.
Then take that number away from your original, for example 105-64=41.
Repeat this until you reach 0.

41-32=9
9-8=1
1-1=0

Decimal	128's	64's	32's	16's	8's	4's	2's	1's
105	0	1	1	0	1	0	0	1

If you add up the values with 1 in their column 1+8+32+64 you get 105.
Now try converting:

Decimal	128's	64's	32's	16's	8's	4's	2's	1's
97
	1	0	0	1	1	0	1	1

Addition

Likely the first way you'd have learnt addition would have been column addition for any non-single digit numbers.
For example if we wanted to add 105 and 27 we'd end up with a table that looked something like this.

	Hundred's	Ten's	Unit's
105	1	0	5
+27		2₁	7
=132	1	3	2

Where as in binary we only have 2 options.

	128's	64's	32's	16's	8's	4's	2's	1's
105	0	1	1	0	1	0	0	1
+27	0₁	0₁	0₁	1₁	1	0₁	1₁	1
=132	1	0	0	0	0	1	0	0

As you can see the ripple of carrying the 1 up moves a lot further in binary than it does in decimal.
Now try 97 + 155:

	256's	128's	64's	32's	16's	8's	4's	2's	1's
97
+155
Carry
=

VHDL File Structure

The individual files contain the building block for all the sub components.

fulladder

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY design_lib;
USE design_lib.all;

-- set up the inputs and outputs for the component
ENTITY halfadd IS
  PORT(
    num1, num2	: IN    std_logic;
    sum, carry	: OUT   std_logic);
END halfadd ;

-- set up the internal combinational logic
ARCHITECTURE halfadder OF halfadd IS
BEGIN
	sum <= num1 XOR num2;
	carry <= num1 AND num2;
END halfadder;

The architecture code links individual components together into larger blocks of logic, using internal signals where necessary.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

LIBRARY design_lib;
USE design_lib.all;

ENTITY busadd IS
  PORT(
    num1    : IN    std_logic_vector(7 DOWNTO 0);
    num2    : IN    std_logic_vector(7 DOWNTO 0);
    sum     : OUT   std_logic_vector(7 DOWNTO 0) := (others=>'0');
    carry   : OUT   std_logic);
END busadd ;

ARCHITECTURE busadder OF busadd IS

SIGNAL ha1carry_int : std_logic_vector(7 DOWNTO 0) := (others=>'0');

COMPONENT halfadd
  PORT (
    num1    : IN    std_logic;
    num2    : IN    std_logic;
    sum     : OUT   std_logic;
    carry   : OUT   std_logic);
END COMPONENT;

COMPONENT fulladd
  PORT (
    num1    : IN    std_logic;
    num2    : IN    std_logic;
    carryin : IN    std_logic;
    sum     : OUT   std_logic;
    carry   : OUT   std_logic);
END COMPONENT;
   
BEGIN
  I0 : halfadd
  PORT MAP (
    num1    => num1(0),
    num2    => num2(0),
    sum     => sum(0),
    carry   => ha1carry_int(0));
    
  -- systematically  generate component instantiate
  G1 : for i in 0 to 6 generate
    C1: fulladd
      port map (
        num1    => num1(i+1),
        num2    => num2(i+1),
        carryin => ha1carry_int(i),
        sum     => sum(i+1),
        carry   => ha1carry_int(i+1));
  end generate;
    carry <= ha1carry_int(7);
END busadder;

Then there is the GPIO test bench to run a simulation of the code.

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;

--! Local libraries
LIBRARY design_lib;
USE design_lib.all;

--! ENTITY/Package Description
ENTITY GPIO_Test is
END ENTITY GPIO_Test;

architecture tb of GPIO_Test is
	SIGNAL	    done	       :	STD_LOGIC;
	SIGNAL	    clk          :	STD_LOGIC;
  CONSTANT    clk_speed    :  TIME  := 20 ns;
  SIGNAL      clk_system   :  STD_LOGIC;
begin

 --! Port map declaration for
	UUT : ENTITY design_lib.fibb
		port map (done	=> done,
			      clk	=> clk_system);
-- set up a process to generate a clock
    Clk_gen: PROCESS is
    begin
        while TRUE loop
            clk_system <= '0';
            wait for clk_speed/2;
            clk_system <= '1';
            wait for clk_speed/2;
        END loop;
        wait;
    END PROCESS;

END architecture tb;

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